Verification with SV - Part 2
Table of Contents
-
Introduction to Testbench Creation
- Overview of the session and goals
- Importance of familiarizing with SystemVerilog patterns -
Understanding Testbench Structure
- Components of a testbench
- Importance of existing code comprehension -
Building the Testbench
- Connecting DUT to the testbench
- Instantiation in SystemVerilog
- Introduction of interface construct in SystemVerilog -
Mod Ports and Clocking Blocks
- Explanation of mod ports
- Understanding clocking blocks -
Implementation of Testbench Top Module
- Structure of the testbench top
- Instantiation of DUT and connections -
Driver and Generator Implementation
- Overview of the push driver
- Handling transactions with the push driver
- Interaction with the mailbox for transactions -
Pop Flow Implementation
- Overview of the pop generator and driver
- Synchronization between push and pop -
Monitor and Scoreboard Functionality
- Implementation of monitors
- Overview of scoreboard functionality -
Test Environment and Program Block
- Structuring the environment for the testbench
- Role of the program block in the testbench -
Test Class Implementation
- Structure of base test class
- Specific test implementation and inheritance -
Running and Debugging Tests
- Running tests and handling results
- Debugging strategies using simulation log files