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Verification with UVM - Part 1

Table of Contents

Introduction to Bootstrapping UVM-based Verification with UART Testbench

Connecting UVM Core Concepts to Practical Application

  • Emphasizing learning patterns and independent code exploration

Goal: Becoming a UVM-aware Verification Engineer

  • Importance of understanding existing testbenches
  • Asking key questions (sequence, monitor, driver, stimulus generation, checks, coverage, reusability)

Understanding the UART DUT

Three Views of a DUT in a SoC

Signal Boundary / Interface View

  • APB Slave Interface (internal to SoC)
  • IRQ pin (internal to SoC)
  • TXD and RXD pins (external, full-duplex)
  • Modem Control Interface (external)
  • Clocks and Resets (internal)

Software View

  • RXD / Data Register (RO, Offset 00)
  • TXD (WO, Offset 00)
  • Interrupt Enable Register (RW, Offset 04)
  • Interrupt Identification Register (RO, Offset 08)
  • FIFO Control Register (WO, Offset 08)
  • Line Control Register (RW, Offset 0C)
  • Modem Control Register (RW, Offset 10)
  • Line Status Register (RO, Offset 14)
  • Modem Status Register (RO)
  • Divisor Latch Registers (Div1, Div2) (RW)

Protocol View

  • APB protocol (deep dive in separate session)
  • UART protocol basics (parallel ↔ serial conversion)

Data Path vs. Control Path

  • Both accessible via APB bus
  • Contrast with high-speed IPs (e.g., USB with AXI for data)

Primary Functionality: Transmission and Reception

Polling Method

  • Read Line Status Register (LSR) continuously
  • Disadvantage: CPU load, overflow risk

Interrupt Method

  • Enable specific interrupts
  • Advantage: Efficient CPU usage, prevents data loss

Test Cases Included in the UART Testbench

Categories of Tests

  • Register Access Tests
  • Normal Operation Tests
  • Error Injection Tests
  • Low Power Tests (not detailed)

Focus Test: Word Format Poll Test

  • Chosen for deep dive analysis

Analyzing the Simulation Log File

Log Structure

  • Testbench topology
  • Traffic messages (UVM logs)
  • End-of-test stats (errors, warnings, info)

Extracting Info via Linux Commands

  • Use grep, wc, etc.
  • Identify register reads/writes (e.g., LCR, TXD, RXD, LSR)

Decoding Values

  • Decode configs (e.g., LCR 0x00)
  • Decode transmitted (TXD) and received (RXD) values

Correlating Log File Information with Waveforms

Transmit Path Visualization

  • Observe register writes (LCR, Div registers)
  • Visualize TXD line (start bit, data, stop bit)

Receive Path Visualization

  • Visualize RXD line (start, data, stop)
  • Polling LSR, checking data ready
  • RXD reads vs. expected values

Overall Correlation

  • Combine logs, waveforms, source code, and spec

Conclusion of Part 1

  • Recap: Interface, software, protocol views of DUT
  • Functional flow (polling vs. interrupt)
  • Test case strategy + log/waveform analysis
  • Transition to Part 2: Building the UVM Testbench