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Verification with UVM - Part 2

Table of Contents

Part 1 Recap: Setting the Stage

Review of UART DUT: Interface and Software Views

Summary of UART Testbench Tests

Deep Dive: Word Format Poll Test

Simulation Log and Waveform Correlation

Key Takeaways

  • APB interface for control/data
  • TXD/RXD for serial data
  • Control via configuration registers

Introduction to UVM Testbench Implementation

Objective and Agenda

  • Understanding how UVM testbench replicates observed functionality
  • Overview of directory structure, components, stimulus, checks, coverage

Quick Refresher on Core UVM Concepts

Test vs. Environment Roles

  • Test drives config and stimulus
  • Environment performs checks and sequences

Components vs. Objects

  • Components: Persistent (test, env, monitor, etc.)
  • Objects: Dynamic (sequence items, sequences)

Configuration Database

  • uvm_config_db for hierarchical configuration passing

UVM Phases

  • Focus: Build, Connect, Run, Check, Report

Factory

  • Creation/registration without deep dive into overrides

Modeling Transactions

  • Sequence item creation using uvm_sequence_item

End of Test Handling

  • Using raise_objection / drop_objection

TLM (Transaction-Level Modeling)

  • For communication between UVM components

Sequences and Sequencers

  • Starting sequences on specific sequencers

UVM Base Class Hierarchy

  • uvm_object
  • uvm_sequence_item → uvm_sequence
  • uvm_component → uvm_test, uvm_driver, uvm_monitor, uvm_env

Utility Classes

  • Config DB, reporting, and logging

Testbench Directory Structure and Organization

Top-Level Folders

  • uart_example/
  • agents/ (APB, UART, Modem)
  • docs/
  • protocol_monitor/
  • rtl/
  • sim/
  • UVM_TB/

Inside UVM_TB Folder

  • env/ – Scoreboards, checkers, coverage
  • reg_model/ – RAL
  • sequences/
  • tb/ – TB top module
  • tests/
  • virtual_sequences/

Code Exploration Techniques

  • find, grep, xargs to explore testbench code

UVM Testbench Core View and Component Interaction

DUT Interfaces

  • APB, TXD, RXD

Agent Instantiation

  • APB (active), UART TX (passive), UART RX (active)

Analysis Components

  • TX Scoreboard
  • RX Scoreboard
  • TX Coverage Model (sampled only on valid TX)

Register Abstraction Layer (RAL)

  • High-level register access, translated by adapters

Virtual Sequencer

  • Orchestrates multiple interface sequences

Environment Configuration

  • Carries interface handles and flags

Test and Environment Interaction

  • Test sets config, launches virtual sequences

SystemVerilog Packages and Code Organization

  • reg_package, uart_agent_pkg, apb_agent_pkg, modem_agent_pkg, env_pkg, etc.
  • env_pkg includes all scoreboards, monitors, checker modules, and env config

Connecting DUT to Testbench (tb_top.sv)

Steps to Connect

  1. Instantiate DUT
  2. Instantiate interfaces (apb_if, uart_if, etc.)
  3. Connect interfaces to DUT ports
  4. Pass interfaces via uvm_config_db

```systemverilog uvm_config_db#(virtual apb_if)::set(uvm_root::get(), "UVM_TEST_TOP", "apb_if", apb_if_inst);