Skip to content

Verification with UVM - Part 3

Table of Contents

Part 1 & 2 Recap: Setting the Foundation

Review of UART DUT and UVM Testbench

  • Interface and software views
  • Overall testbench structure
  • run_test() and uvm_config_db basics

Focus for Part 3

  • What happens in the Build Phase and Connect Phase

Understanding the UVM Phasing Flow

Session Approach and Goal

  • Phase-by-phase walkthrough
  • Trace "Word Format Poll Test" execution (TX two chars, RX two chars)

The Build Phase: Top-Down Construction

Overview of Build Phase

  • First phase, flows top-down
  • Constructs hierarchy from test to agents

Base Test Build (uart_test_base)

  • run_test() invokes test class
  • Test extends uart_test_base
  • Uses UVM_COMPONENT_UTILS for factory registration
  • Key elements:
  • Handles for env, env config, RAL model, and agent configs
  • Factory-based creation of components
  • Set/Get of virtual interfaces using uvm_config_db
  • Set agent configs into env config
  • Create environment via factory
  • Set env config into uvm_config_db for environment

Register Abstraction Layer (RAL) Model Deep Dive

Purpose and Benefits

  • Abstract memory-mapped register access
  • Portable tests independent of address/bus
  • Supports front-door/back-door access
  • Core unit: uvm_reg_bus_op

Modeling Registers and Fields

  • Extend uvm_reg, use UVM_OBJECT_UTILS
  • Declare fields using uvm_reg_field (optional rand)
  • Use build() to create and configure fields

Mapping Registers in uart_reg_block

  • Extend uvm_reg_block
  • Declare handles for all registers and uvm_reg_map
  • In build():
  • Create register objects
  • Call configure(this)
  • Create m_map, call add_reg() to map to offsets
  • Optionally lock model

Writing the Adaptation Layer (reg2apb_adapter)

  • Extend uvm_reg_adapter
  • Implement:
  • reg2bus(): Convert generic op to APB item
  • bus2reg(): Convert APB item back to generic op

Environment Build (uart_environment)

  • Handles for config, agents, scoreboards, RAL adapter/predictor
  • Key build actions:
  • Extract env config from uvm_config_db
  • Create agents using factory
  • Set individual agent configs in uvm_config_db
  • Create reg predictor and adapter
  • Construct scoreboards, coverage models
  • Build continues into agent subcomponents (driver, monitor, sequencer)

The Connect Phase: Bottom-Up Wiring

Overview and Purpose

  • Happens after Build
  • Bottom-up wiring of ports
  • Establishes TLM connections

TLM Ports in Connect Phase

  • Analysis Port: One-to-many, for monitor → subscribers
  • Sequence Item Port: Driver → sequencer (covered later)

Environment Connect Phase Details

  • RAL connections:
  • m_map.set_sequencer() to link to APB sequencer
  • Configure reg predictor with map and adapter

  • Monitor's ap.connect() to reg predictor

  • Scoreboard connections:

  • Agent monitor ap.connect() to scoreboard FIFO

  • Scoreboard ap.connect() to coverage models

  • All components must be built before being connected

  • Transition to Run Phase follows (next session)